This invention relates to the field of electrically alterable read-only semiconductor memories. More specifically, this invention is described with respect to the type of memory that utilizes floating gate field effect transistors as storage cells. Each storage cell, which may also include a selection transistor therein, stores one bit of information. Typically, eight bits or eight storage cells are logically grouped together to form a byte. The bytes are organized in an array of rows and columns. Thus, if 16 columns are utilized with each column containing 128 rows, an array of 2,048 bytes is produced on a single semiconductor chip.
The prior art recognizes the desirability for being able to clear these memories one byte at a time if desired. Such a feature permits the user to change the contents of a single eight-bit byte by erasing only that byte and then entering new data into the byte. Without the feature, it would be necessary to empty the entire contents of the memory into a temporary buffer memory where the required byte could be altered and then to rewrite all 2,048 bytes back into the semiconductor memory chip.
One typical prior art approach for clearing a single byte involves positioning a special transistor in the vicinity of each byte on the chip, operable in response to an X address signal and a Y address signal, to clear only the eight storage cells in the selected byte. The disadvantage of this prior art approach is that 2,048 additional transistors are required to operate the 16 by 128 byte array mentioned above. Furthermore, each column of bytes requires an extra metal line to supply the Y address signal to the special transistors associated with each byte in that column. These additional transistors and metal lines reduce the density of parts on the chip and require larger chips to accommodate the same storage capacity. The present invention, however, permits greater density in the memory array by providing a circuit wherein the selection devices necessary to select an individual byte for clearing may be positioned at the periphery of the array rather than dispersed throughout the array. As a result, each column may operate with one less signal line and one less transistor per byte.